The present invention is directed, in general, to a method of testing a gate oxide located on a semiconductor wafer and, more specifically, to a method of determining the interface trapped charge at the substrate/dielectric layer interface by a contactless charge technique.
The use of and different methods for manufacturing semiconductors have reached phenomenal proportions over the last decade. Equally phenomenal has been the ever decreasing device size of the semiconductors in general, including gate oxide thickness. It is particularly desirable to make the thickness of the gate oxide as small as possible because the drive current in semiconductor devices increases with decreasing gate oxide thickness. Thus, the on-going trends toward ever thinner gate oxides are making tight in-line monitoring of gate oxide quality and uniformity even more critical to semiconductor manufacturers, particularly now that gate oxide thickness is approaching a size less than 25 nm. The quality of the gate oxide can be determined from a number of characteristics, such as charge contamination (Qm), the degree of density of interface traps (Dit) and the flatband voltage (Vfb).
Present techniques for determining these characteristics include techniques, such as charge pumping, Capacitance-Voltage (CV) testing, and Corona Oxide Semiconductor (COS) wafer testing. Each one of these techniques, however, suffer from its own disadvantages.
Conventional charge pumping involves pumping charge into a completed metal oxide field effect transistor (MOSFET) to obtain interface trap information. While charge pumping has been used successfully, it requires a fully completed MOSFET device. Because a full MOSFET structure is required, more time is required to obtain the desired data regarding the quality of the gate oxide. In the interim, hundreds of product may have been produced which are later found to have a poor quality gate oxide, making them unacceptable for sale. Additionally, when testing a fully completed MOSFET device, the gate oxide information is buried in subsequent complementary metal oxide semiconductor (CMOS) processing steps, and so intrinsic gate oxide quality is hard to deconvolute on a fully processed wafer. For example, during normal processing steps, the silicon/oxide interface can become passivated with hydrogen. This passivation can mask the initial quality of the gate oxide when tested with the charge-pumping technique such that data regarding the initial quality of the gate oxide is extremely difficult to obtain.
C-V testing is also another well known method for testing semiconductor devices. C-V testing is based on measuring the metal oxide semiconductor (xe2x80x9cMOSxe2x80x9d) capacitance as a function of applied bias, to gain important information about the quality and reliability of gate oxides. However, while C-V techniques are well known and of relatively low cost, the procedure suffers from the disadvantage that the process has a slow test turnaround time. The slow turnaround time is largely due to the added aluminum evaporation or photolithographic patterning required for the test capacitor sample, which slows down production. In addition, C-V techniques require a standard sample, against which the test results are compared. This, of course, can introduce unacceptable error into the results when the actual product begins to drift significantly from the standard.
Corona Oxide Semiconductor (xe2x80x9cCOSxe2x80x9d) wafer testing is also being extensively used. This technique requires no physical contact with the wafer, so the device""s electrical characteristic data can be obtained without the added processing time and cost associated with forming a complete MOSFET device. In conventional COS, a variety of charge-trapping parameters of the dielectric can be measured, such as charge contamination (Qm), the degree of density of interface traps (Dit), the flatband voltage (Vfb) and the level of mobile charge carrier. The draw back to the COS technique, however, is that it requires the use of a monitor wafer, similar to the C-V technique. As previously stated, there is a strong possibility of data errors when the actual product being tested begins to drift significantly from the monitor wafer. In addition, however, the monitor wafer itself is also subject to hydrogen drift over a period of time. In drift, the hydrogen can occupy the dangling bond sites that exist in the oxide, which can affect the quality of the oxide and also give erroneous trap charge data.
Thus, as seen from the foregoing conventional testing processes, there is not presently a method of determining interface trap information without either encountering significant downtime or drift problems in the monitor wafer, which decreases in accuracy over a period of time.
Accordingly, what is needed in the art is a method of testing the initial quality of a silicon/silicon dioxide interface without the disadvantages associated with the above-discussed techniques.
To address the above-discussed deficiencies of the prior art, the present invention provides a method of determining a trap density of a semiconductor substrate/dielectric interface. In one advantageous embodiment, the method comprises measuring a current within a semiconductor substrate resulting from a flow of carriers from traps located near the interface, wherein the measured current is a function of the number of traps located at the interface. The trap density can be determined as a function of the measured current.
The method may further include a step of filling interface traps. In one aspect, the traps are filled by depositing a charge on a surface of the dielectric layer to form an inversion region, which causes the minority carriers to move toward the substrate/dielectric interface and fill the interface traps in the dielectric. In another aspect, a deep depletion region is formed by quickly depositing more of the same charge used to form the depletion region. This particular embodiment may further include forming an accumulation region within the deep depletion region. The accumulation region may be formed by depositing a charge opposite to the charge previously placed on the dielectric through an opening in a guard ring and onto the dielectric to bring a portion of the deep depletion region into accumulation. This effectively forms pseudo or transient source and drain regions into which carriers flow during the accumulation phase.
A current is generated by the formation of the accumulation region when minority carriers that are trapped in the interface recombine with the majority carriers. Alternatively, the current may be formed by allowing the semiconductor substrate to return to a flatband condition, at which point the minority carriers recombine with the majority carriers. In either case, a current results when the minority carriers leave the traps and recombine with the majority carriers. From this current, the interface trap charge can be determined. The dopant of the substrate may, of course, vary. For example, the substrate may be doped with a p-type dopant, and in such instances, the charge deposited on the substrate is a positive charge and the opposite charge is a negative charge. Alternatively, the dopant may by an n-type dopant, and in such instance the charge deposited on the substrate is a negative charge and the opposite charge is a positive charge.
In those embodiments where the accumulation region is formed in the deep depletion region, pseudo or transient source/drain structures are formed in the wafer substrate without implants and without the need for metal contacts. Moreover, the present invention allows for in-line, fast testing of gate oxide quality as it is being processed. Quick turn around times for determining the quality of the dielectric layer are provided, which in turn, provides readily available processing data that can be used to correct any deficiencies in the fabrication process that affect the quality of the dielectric layer. As a result, fewer wafers are scrapped and time is saved in the overall fabrication process, resulting in a more cost effective process. Thus, in one aspect, the present invention provides a method of determining electrical characterizations of an substrate interface within a semiconductor wafer without the need of fabricating a complete MOSFET device or relying on a monitor wafer.
The present invention provides another embodiment in which traps located at the interface are filled with minority carriers by forming a depletion region within a substrate. At least a portion of the depletion region is collapsed to either flatband or accumulation conditions. Then, a trap density is determined as a function of a current resulting from a recombination of majority carriers with the minority carriers that occurs at accumulation or flatband conditions. Preferably, a portion of the substrate is brought into accumulation by placing a guard ring over the dielectric layer and placing a charge opposite to the one used to form the depletion region is deposited on the dielectric layer through an opening in the guard ring. The opposite charge causes the majority carrier to move to the interface, and when sufficient majority carrier are present, the minority traps move from the traps and recombine with the majority carrier. The movement of the minority traps results in a current flow within the substrate that can be use to determine the trap density of the dielectric layer.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.